ECCE - 2027

Modeling and Exploration of RISC-V architecture with High Level Synthesis

Efficient design space exploration (DSE) of RISC-V architectures is a critical and challenging task, particularly in the domain of electrical, computer, and communication engineering, where optimizing performance, power, and area (PPA) is paramount. By coupling high-level modeling and synthesis, significant improvements in design quality and productivity can be achieved. High-Level Synthesis (HLS) enables the extraction of PPA information from higher levels of abstraction, streamlining architectural DSE and facilitating innovative design strategies for dense-control applications such as RISC-V processors.

In this presentation, we propose ASLP, a novel technique to enhance HLS for synthesizing dense-control designs, achieving dynamic loop pipelining�a feature typically reserved for manual processor design workflows. This advancement paves the way for HLS-based modeling of RISC-V architectures, offering a foundation for PPA-constrained DSE frameworks and aligning with the themes of advanced engineering solutions discussed at ECCE 2025. By integrating ASLP into the HLS flow, we demonstrate how these techniques can streamline processor design while maintaining high efficiency and scalability. Future work, such as incorporating machine learning into this framework, promises to further accelerate exploration and enhance outcomes, making this research a valuable contribution to the ongoing advancements in electrical, computer, and communication engineering.

Prof. Ray C.C. Cheung is currently the Associate Provost at City University of Hong Kong, and Professor in the Department of Electrical Engineering. He received the BEng and MPhil degrees in computer engineering and computer science and engineering at CUHK, and the PhD degree and DIC in computing at Imperial College London, United Kingdom. He was with Stanford University and UCLA in the summer as a visiting scholar. He received the Hong Kong Croucher Foundation Fellowship for his postdoctoral study in the Electrical Engineering Department, UCLA. He worked as a visiting research fellow in the Department of Electrical Engineering, Princeton University. His research team, CityU Architecture Lab for Arithmetic and Security (CALAS), focuses on secure processor design, reconfigurable trusted computing, AIoT, applied cryptography, and high-performance VLSI designs. He also co-founded the Xilinx Research Lab at CityU in the Department of Electrical Engineering. He is the founding technical chair at the IEEE International Conference on Field-Programmable Technology (FPT) in Hong Kong in 2002, the general chair of Applied Reconfigurable Computing (ARC) 2012 in Hong Kong, the general co-chair of FPT in Hong Kong in 2022. He is a senior member of the IEEE, the IEEE HK Section Chair 2024, the past chair of IEEE HK Section CAS/COM Joint Chapter, the past chair of IEEE Industrial Electronics Society, Technical Committee, Electronic System-on-Chip (eSoC), the past vice-chair of IEEE HK Section Computer Chapter, the current IEEE HK Section Student Branch Counsellor (CityU), the current IEEE HK Section Treasurer, and CityU Underwater Robotic Team supervisor. He is the author/co-author of more than 250 International journal and conference papers. He is also the chairman of Hong Kong STEM Education Alliance, and the founder of Hour of Code Hong Kong.